[ #g͍ ddlZddlZddlZddlZddlZddlmZmZmZm Z m Z m Z ddl m Z ddlmZddlmZmZddlmZddlmZddlmZej2eZ Gd d ej8ZGd d ej<ZGd deZ Gdde eZ!GddeZ"Gdde"eZ# GddZ$GddZ%dde&de de&de&fdZ'y)N)OptionalDictAnyListIterableTuple)Enum) classproperty) interfaces exceptions) requirements)linear) path_joinc eZdZy)AArch64ExceptionN__name__ __module__ __qualname__R/home/panchajanya/Development/work/volatility3/volatility3/framework/layers/arm.pyrr,rrceZdZdZej ddiddiejjjZ dZ e dzZ dZ e Z gdgdgd d Z d=d ejj d ededeeeefdd f fd Zd>dZededededeefdZedededeeefdZdedeeeeffdZdedeeeeffdZe jBddedee"fdZ# d?ded ed!ede$eeeeeeffd"Z% d?ded ed!ede$eeeeeeffd#Z&deefd$Z'd@ded edefd%Z(dedefd&Z)d'edefd(Z*e+e jBdefd)Z,e+e jBdefd*Z-e+e jBdefd+Z.e/e jBdefd,Z0e+e jBdefd-Z1e+e jBdefd.Z2 d?d/e3d!edefd0Z4ed1e5de5fd2Z6d3edefd4Z7d3edefd5Z8e9 d=d6ed7ed8ed9eedef d:Z:e+deefd;Z;edeejxjzfd<Z>xZ?S)AAArch64zTranslation Layer for the Arm AArch64 memory mapping. This layer can be instantiated in two contexts : Low space (user land), High space (kernel land). architecturemappedT@))30)/')&)) ))r r").$)#)))r *))r&))r3rNcontext config_pathnamemetadatareturnc( t|||||i|_tjj tj j tjj fD]:}|jj|s|j||j|<<|j|j|_ |jd|_ |jjdd|_ |jjdd|_|jd|_|jd|_|j#tj j$|_|j#tjj(|j#tjj*g|_t.j1|j#tjj2t.j5|j#tjj6g|_t;|j |j&k(|_d|j,|j<z |_|j8|j<|_ |j@d z|_!|jBjEd z |_# |j>d krd nd|_$|jHr,|j@d vrd|_%n|j@dk(rd|_%|jM|j@|j>|_'|jQ|j@|jN|jH|_)|jU|_+|jYd |jZzd z |jZ|j>d|_.t_j`|j|_1|jB|jbz|_2|j#tjjfd }|rt.ji||_5nd|_5|jr|jmyy)N)r5r6r7r8 entry_format layer_debugFtranslation_debug memory_layerpage_map_offsetrir3Tr4r3) r)r)r)7super__init__ _cpu_regs AArch64RegMapTCR_EL1r TTBR1_EL1ID_AA64MMFR1_EL1configget_map_reg_values_cpu_regs_mapped _entry_format _layer_debug_translation_debug _base_layer_page_map_offset_read_register_fieldBADDR_page_map_offset_kernelT0SZT1SZ _ttbs_tnszAArch64RegFieldValues_get_ttbr0_el1_granule_sizeTG0_get_ttbr1_el1_granule_sizeTG1_ttbs_granulesint_virtual_addr_space _ttb_bitsize _ttb_granule _page_size bit_length_page_size_in_bits _is_52bits _ta_51_x_bits_determine_ttb_lookup_indexes_ttb_lookup_indexes_determine_ttb_descriptor_bits_ttb_descriptor_bits_get_virtual_addr_range_virtual_addr_range_mask_bits_per_register_canonical_prefixstructcalcsize _entry_size _entry_numberHAFDBS_get_feature_HAFDBS _feat_hafdbs_print_layer_debug_informations)selfr5r6r7r8registerhafdbs __class__s rrEzAArch64.__init__Ks 4(    ! ! * *  # # , ,  * * 3 3 H{{x(+/;;x+@x( !% 4 4T^^ D![[8 KKOOM5A"&++//2Eu"M;;~6 $ ,= >'+'@'@  # # ) )( $  % %m&;&;&@&@ A  % %m&;&;&@&@ A  " = =))-*?*?*C*CD  " = =))-*?*?*C*CD   $'  ! !T%A%A A$  1I1I!JJ //0H0HI++d2"&//"<"<">"B #'"3"3b"8$e ??  G+%+"""b(%-"$(#E#E   t00$  %)$G$G   t77% !$(#?#?#A !% $)) )Q .  # #    " "??4+=+=>!__0@0@@**=+I+I+P+PRVW  5 I I& QD  $D      0 0 2 rc ftjd|jtjd|jrdndtjdt |j Dcgc] }t |c}tjd|jtjd|jd|jtjd t |jtjd |jycc}w) Nz Base layer : zVirtual address space : kerneluserz Virtual addresses space range : z Page size : TzSZ : zPage map offset : zTranslation mappings : ) vollogdebugrRratuplermhexrcrbrSrj)rzxs rryz'AArch64._print_layer_debug_informationss }T%5%5$678 &43K3KxQW&X Y   .udFbFbFd5ec!f5e/f.g h   |D$5$5#678 q112%8I8I7JKL )#d.C.C*D)EFG .t/G/G.HIJ6fs0D. ttb_granulettb_lookup_indexes is_52bitsc&|dvr|rdnd|ddfS)zReturns the descriptor bits to extract from a descriptor (high and low) Example with granule = 4 kB without 52 bits : (47,12) Example with granule = 16 kB and 52 bits : (49,14) rA1r"r@r)clsrrrs rrkz&AArch64._determine_ttb_descriptor_bitss)(YBB r "1 %  r ttb_bitsizecx|j|Dcgc] }||dkDr|}}|dz |ddf|d<|Scc}w)aReturns the bits to extract from a translation address (highs and lows) Example with bitsize = 47 and granule = 4 kB : indexes = [(51, 48), (47, 39), (38, 30), (29, 21), (20, 12)] result = [(46, 39), (38, 30), (29, 21), (20, 12)] r@r)_granules_indexes)rrrindexindexess rriz%AArch64._determine_ttb_lookup_indexess^..{; U1X%   "Aowqz!}5  s7virtual_offsetc|j|\}}}|j||dz d}||z}|d|z|jfS)zTranslates a specific offset based on paging tables. Returns the translated offset, the contiguous pagesize that the translated address lives in and the layer_name that the address lives in r@r)_translate_entryrorR)rzr table_addressposition_offset_within_pagephysical_offsets r _translatezAArch64._translatesT&*%:%:>%J" x!ZZ1 aH'*<<8 T-=-===rc|jj|j}|j|dd}||jk7r!t j |j||j}t|jdz }t|jD]\}\}}|j|||} tj|j|j|| |j zz|j \} d}|j"rC|j| |j$d|j$d} | d| j'z z}|j| dd} ||kr{| dk(rv||j| |j(d|j(d|j(dzz}|j+|*t j,|j||| ||kr-| dk(r(||j| |j(d||zz}np||k(rG| dk(rB||j| |j(d|j(d|j(dzz}n$t j,|j||| |j.rYt0j3dt5|d t5|d t5|j|dz dd t5 | fS) zTranslates a virtual offset to a physical one within this segment Returns the translated address, the maximum offset within the block and the page the translated address lives in 7 layer_nameinvalid_addressr@r4)rr invalid_bitsentryzVirtual z lives in page frame z at offset z with descriptor )r5layersrRrorar InvalidAddressExceptionr7rSlenrj enumeraterrunpackrOread_register_sizergrhrerl_get_valid_tablePagedInvalidAddressExceptionrQrrr) rzr base_layer ttb_selectorr max_levellevelhigh_bitlow_bitr descriptorta_51_xdescriptor_types rrzAArch64._translate_entrysj \\(()9)9: zz."b9  433 34499 .  -- 001A5 *3D4L4L*M &E&HgJJ~xAE"MM""!UT-@-@%@A4CVCVMZ M**&&q)&&q) !(B1C1C1E,E F #jjQ:Oy _%<JJ"11!411!4 003 4 ((7?$AA#'99(6%,( "$'>JJ"11!4   )#4(?JJ"11!411!4 003 4 !==#yy$2!($ {+NH  " " LL3~.//DSEWDXXcdghlhrhrtBDKLMDMOPiQeRdSSdehisetduv gz11ri base_addressc|jjj|j||j}||d|j |j zk(ry|S)zJExtracts the translation table, validates it and returns it if it's valid.N)_contextrrrR page_sizertru)rzrtables rrzAArch64._get_valid_tableMsZ $$))   lDNN  E,D,,-0B0BB B roffsetlength ignore_errorsc#Kdx}x}x}x}}|j|||D]?\}} } } } |||z|k7s ||z| k7s|| k7r| |||||f|}| }| }| }| }6|| z }|| z }A|||| | |||||fyyyyyyw)zReturns a sorted iterable of (offset, sublength, mapped_offset, mapped_length, layer) mappings. This allows translation layers to provide maps of contiguous regions in one layer N)_mapping) rzrrrstashed_offsetstashed_mapped_offset stashed_sizestashed_mapped_sizestashed_map_layersize mapped_offset mapped_size map_layers rmappingzAArch64.mappingYs   .  @S CG== FMD ?FD-i&"\1V;),??=P%2"-(,8MObduuu!'(5%# &1#$-!$ #{2#+D 0  &%1(#/!- ,0EGZ\mm m.0)2 'sA9A;c#.K|dk(r` |j|\}}}|jj|j|st j || |||||fy|dkDr |j|\}}}t |||zz |} |jj|j|| st j || || || |f|| z}|| z }|dkDryy#tj $r|sYywxYw#tjtj f$rb} |st| tjrd| jzdz } nd|jzdz } | dz|| zz } || z}|| z }Yd} ~ d} ~ wwxYww)aReturns a sorted iterable of (offset, sublength, mapped_offset, mapped_length, layer) mappings.This allows translation layers to provide maps of contiguous regions in one layer. A bit of lexical definition : "page" means "virtual page" (i.e. a chunk of virtual address space) and "page frame" means "physical page" (i.e. a chunk of physical memory). What this is actually doing : - translate a virtual offset to a physical offset - determine the page size the virtual offset lives in (page_size) - based on the position of the offset in the page, calculate how many bytes to add to get to the end of the page (chunk_size) - add the chunk_size to the virtual offset, so that we can point to the start of the next page Example (assume page size is 4096): -> 0xffff800000f92140 lives in page 0xfffffc0000170640 at offset 0x140, which maps to page frame 0x45c19000 at offset 0x140 -> 4096 - 0x140 = 3776 -> 0xffff800000f92140 + 3776 = 0xffff800000f93000 -> we know the start of the next page is at virtual offset 0xffff800000f93000, so we can directly jump to it (no need to translate every byte in between) -> 0xffff800000f93000 lives in page 0xfffffc0000087040 at offset 0x0, which maps to page frame 0x421c1000 at offset 0x0 -> 4096 - 0x0 = 4096 -> 0xffff800000f93000 + 4096 = 0xffff800000f94000 etc. while "length" > 0 rrNr@) rrris_validr rminr isinstancer page_shift) rzrrrrrr chunk_offsetr chunk_sizeexcpmask length_diffs rrzAArch64._mappings2 Q; /3v/F, q*}}++J7@@O$<<#-}P&-C Cqj %6:oof6M3 i lY.F!GP }}++J7@@ *%<<#-|0j, JNN*$*$=qj 55 $ "7722 &%dJ$K$KL!2!22a7D0A5D"Qh&4-8 +%+%! &s[FAC1F.A'D F/F1D F D  F #F0AF F FFc|jdk(r d}d|jdz z}||dz z}||fSd}d|jdz z}||dz z }||fS)zVReturns the virtual address space range for the current context (user or kernel space)rr@l)rarb)rz ttb_startttb_sizettb_ends rrmzAArch64._get_virtual_addr_ranges|  # #q (IT..23H8a<0G 7##  GT..23H8a<0I7##rc  t|j||Dcgc]0\}}}}}|jj|j |2c}}}Scc}}}w#t j $rYywxYw)zPReturns whether the address offset can be translated to a valid address.F)allrrrrr r)rzrrrrlayers rrzAArch64.is_valids :>ff9U51mQMM((/88G  11  s"A"5A A"A""A87A8cH|j|j|dS)z2Returns whether the page at offset is marked dirtyr)_page_is_dirtyr)rzrs ris_dirtyzAArch64.is_dirtys#""4#8#8#@#CDDrrc\|jrt|dzxr|dz Std)uw Hardware management of the dirty state (only >= Armv8.1-A). General documentation : https://developer.arm.com/documentation/102376/0200/Access-Flag/Dirty-state Technical documentation : [1], see D8.4.6, page 5877 : "Hardware management of the dirty state" [1], see D8-16 and page 5861 : "Stage 1 attribute fields in Block and Page descriptors" > For the purpose of FEAT_HAFDBS, a Block descriptor or Page descriptor can be described as having one of the following states: • Non-writeable. • Writeable-clean. • Writeable-dirty. [1], see D8-41, page 5868 : AP[2] | Access permission -------|------------------ 0 | Read/write 1 | Read-only AF=0. Region not accessed. AF=1. Region accessed. l@zHardware updates to Access flag and Dirty state in translation tables are not available. Please try using a software based implementation of dirty state management.)rxboolNotImplementedError)rzrs rrzAArch64._page_is_dirtys?2   '*FUf5E0FG G%w rc|jS)zlPage shift for this layer, which is the page size bit length. - Typical values : 12, 14, 16 )rfrzs rrzAArch64.page_shifts &&&rc|jS)zZPage size for this layer, in bytes. - Typical values : 4096, 16384, 65536 )rdrs rrzAArch64.page_sizes rc"|jdz SzPage mask for this layer.r@rrs r page_maskzAArch64.page_mask s!#$$rc|jS)z[Returns the bits_per_register to determine the range of an AArch64TranslationLayer.)rprs rbits_per_registerzAArch64.bits_per_register&s %%%rc |jdS)Nrrnrs rminimum_addresszAArch64.minimum_address-''**rc |jdS)Nr@rrs rmaximum_addresszAArch64.maximum_address2rrregister_fieldcvt|} |j|S#t$r|rYyt|dwxYw)Nz8 register field wasn't provided to this layer initially.)strrNKeyError)rzrrreg_field_paths rrTzAArch64._read_register_field7sR^, ((8 8 !""Z[  s  88registers_valuescDi}tjttjD]r\}}t |t s||j vs*||}|D]?}t||j}|j\}} |j||| } | ||<At|S)aGenerates a dict of dot joined AArch64 CPU registers and fields. Iterates over every mapped register in AArch64RegMap, check if a register value was provided to this layer, mask every field accordingly and store the result. Example return value : {'TCR_EL1.TG1': 3, 'TCR_EL1.T1SZ': 12, 'TCR_EL1.TG0': 1, 'TCR_EL1.T0SZ': 12, 'TTBR1_EL1.ASID': 0, 'TTBR1_EL1.BADDR': 1092419584, 'TTBR1_EL1.CnP': 0} ) inspect getmembersrGisclass issubclassr keysrr7valuero) rr masked_trees mm_cls_namemm_cls reg_valuefield dot_joinedrr masked_values rrMzAArch64._map_reg_valuesDs #*#5#5mW__#U K&$'K;K;P;P;R,R,[9 #E!*; !CJ(- %Hg#&99Y'#JL/;L, $$Vraddrc|j|jkr||jzS|d|jdz zkr|S|j||jd|jzS)z[Canonicalizes an address by performing an appropiate sign extension on the higher addressesr@r)rprb address_maskrorqrzrs r canonicalizezAArch64.canonicalize\sh  " "d&7&7 7$+++ + Q$++a// 0Kzz$ 1 1158N8NNNrcN|d|jdz zkr|S||jz S)zRemoves canonicalization to ensure an adress fits within the correct range if it has been canonicalized This will produce an address outside the range if the canonicalization is incorrect r@)rbrqr s rdecanonicalizezAArch64.decanonicalizeds2 1))A-- .Kd,,,,rrrrshiftcJ||}d|dzzdz }d|zdz }||z }||z|z S)zAReturns the bits of a value between highbit and lowbit inclusive.r@r)rrrr high_masklow_maskrs rroz AArch64._maskmsH =E8a<(A- LA%8# &&rc|jgS)zRReturns a list of the lower layer names that this layer is dependent upon.)rRrs r dependencieszAArch64.dependenciesys  !!rcftjddtjdddtjdddtjd d d d tjd d dd tjdd dtjdd dtjt j jddtjt jjddtjt jjd dd g S)Nr>F)r7optionalr?zJDTB of the target context (either "kernel space" or "user space process").)r7r descriptionr;zOFormat and byte order of table descriptors, represented in the "struct" format.r<TzLSpecify if debugging informations about the layer should be printed to user.)r7rrdefaultr=zHSpecify if translation debugging informations should be printed to user.kernel_virtual_offsetz ASLR offset kernel_bannerz\Kernel unique identifier, including compiler name and version, kernel version, compile time.zTCR_EL1 registerzTTBR1_EL1 registerzID_AA64MMFR1_EL1 register) r TranslationLayerRequirementIntRequirementStringRequirementBooleanRequirementrGrHrrIrJrs rget_requirementszAArch64.get_requirementss.  4 4#e   ' '&h   * *#m   + +"j    + +(f    ' ',t   * *$z   ' '"**33.   ' '",,550   ' '"33<<7  Y2 2 r)N)r9NF)r@)@rrr__doc__ collectionsChainMapr rTranslationLayerInterface_direct_metadatarpr _maxphyaddr _maxvirtaddrrr5ContextInterfacerrrrrEry classmethodr`rrrkrrirr functools lru_cachebytesrrrrrmrrrpropertyrrrr rrrr rTdictrMr r staticmethodror configurationRequirementInterfacer __classcell__r}s@rrr0s ,{++ # 433DD '1,NKL > 4 *.2 a3##44a3a3 a3 4S>* a3  a3F   36 CG s  ",/ eCj $ > >sC}1E >\2s\2uS#s]7K\2|Y S Xe_  ?D*n*n#&*n7;*n %S#sC/0 1*nZ?DD%D%#&D%7;D% %S#sC/0 1D%L$ s$" s C  EsEtE C D DY'C'' Y3 Y%3%%Y&#&& Y+++Y+++;@ " 37   t.OOO-3-3-HL ' '! ',/ '8@  '  ' '"d3i"" 3 j&>&>&S&S!T3 3 rrc(eZdZdedeffd ZxZS)LinuxAArch64Mixinrr9cnt|dz} t| |}|xs|S#t$r|cYSwxYw)aReturns whether a particular page is dirty based on its (page table) entry. The bit indicates that its associated block of memory has been modified and has not been saved to storage yet. The following is based on Linux software AArch64 dirty bit management. [2], see arch/arm64/include/asm/pgtable-prot.h#L18 [2], see pte_wrprotect() [3], see page 12-25 https://lkml.org/lkml/2023/7/7/77 -> Linux implementation detail lrrDrrrzrsw_dirtyhw_dirtyr}s rrz LinuxAArch64Mixin._page_is_dirtysG)* w-e4H'x '" O s & 44rrrr`rrr2r3s@rr5r5sCDrr5c eZdZy) LinuxAArch64Nrrrrr=r=rrr=c(eZdZdedeffd ZxZS)WindowsAArch64Mixinrr9c~t|dzxr|dz } t| |}|xs|S#t$r|cYSwxYw)aReturns whether a particular page is dirty based on its (page table) entry. The bit indicates that its associated block of memory has been modified and has not been saved to storage yet. The following is based on the Windows kernel function MiMarkPteDirty(). Capabilities are initialized in MiInitializeSystemDefaults(). When marking a PTE dirty, MiMarkPteDirty() will: - set AF to 1 (ACCESSED) manually if hardware does not support it; - set AP to 0 (RW) manually if hardware does not support it. In the end, we need to detect if the DBM is software (56) or hardware (51), and if in any scenario the AP bit is set to 0. lrr7r8s rrz"WindowsAArch64Mixin._page_is_dirtysT'*FUf5E0FG w-e4H'x '" O s . <<r;r3s@rr?r?sCDrr?ceZdZdZdZeejdefdZ eejdefdZ eejdefdZ y)WindowsAArch64zAs Windows (AArch64) page size is constant, we take advantage of the @classproperty decorator, because @property is dynamic and breaks static accesses in windows automagic. ir9c<|jjdz S)z=Page shift for this layer, which is the page size bit length.r@)rrers rrzWindowsAArch64.page_shifts}}'')A--rc|jS)z#Page size for this layer, in bytes.)_windows_fixed_page_sizers rrzWindowsAArch64.page_sizes+++rc"|jdz Srrrs rrzWindowsAArch64.page_masks"##rN) rrrr!rEr r*r+r`rrrrrrrBrBs &Y.3..Y,#,,Y$#$$rrBcheZdZdZGddeZGddeZGddeZGdd eZy ) rGz List of static Enum's, binding fields (high bit, low bit) of AArch64 CPU registers. Prevents the use of hardcoded string values by unifying everything here. Contains only essential mappings, needed by the framework. c&eZdZdZdZ dZ dZ dZy)AArch64RegMap.TCR_EL1zTCR_EL1, Translation Control Register (EL1). The control register for stage 1 of the EL1&0 translation regime. [1], see D19.2.139, page 7071 )r%)r'r3)rCr/)rN)rrrr!r^rXr\rWrrrrHrI s) )m)mrrHc eZdZdZdZ dZ dZy)AArch64RegMap.TTBR0_EL1apTTBR0_EL1, Translation Table Base Register 0 (EL1) Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL1&0 translation regime, and other information for this translation regime. [1], see D19.2.155, page 7152 [1], see D19.2.152, page 7139 ?r!r"r@rrNrrrr!ASIDrUCnPrrr TTBR0_EL1rM! 9)rrUc eZdZdZdZ dZ dZy)AArch64RegMap.TTBR1_EL1aSTTBR1_EL1, Translation Table Base Register 1 (EL1) Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the higher VA range in the EL1&0 stage 1 translation regime, and other information for this translation regime. [1], see D19.2.155, page 7152 rNrPrQNrRrrrrIrX&rVrrIceZdZdZdZy)AArch64RegMap.ID_AA64MMFR1_EL1z_ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1. [1], see D19.2.65, page 6781)rrN)rrrr!rvrrrrJrZ3s (PrrJN) rrrr!r rHrUrIrJrrrrGrGs; n$ n D  D Q4QrrGc eZdZe d dededefdZededefdZed dedefdZ e d dedede efdZ y ) rZr lookup_tablereverse_lookupc|r#|jDcic]\}}|| }}}|j|ddk7r||Std|d|cc}}w)NValue z+ could not be mapped inside lookup_table : )itemsrLr)rrr\r]kvs r _table_lookupz#AArch64RegFieldValues._table_lookup<so -9-?-?-ABTQAqDBLB   E4 (D 0& &J<.Y  Cs Ar9c |dk\S)z~ Hardware updates to Access flag and Dirty state in translation tables. [1], see D19.2.65, page 6784 rr)rrs rrwz)AArch64RegFieldValues._get_feature_HAFDBSIs }rc4dddd}|j|||S)z1 Granule size for the TTBR0_EL1. r4rr3)rr@rrcrrr]r\s rr[z1AArch64RegFieldValues._get_ttbr0_el1_granule_sizeQs+     nEErc4dddd}|j|||S)z1 Granule size for the TTBR1_EL1. r3r4r)r@rrrfrgs rr]z1AArch64RegFieldValues._get_ttbr1_el1_granule_size]s+    nEErNr ) rrrr)r`r.rrcrwr[rr]rrrrZrZ;sDI  '+ =A   F FT F F05 F F)- F # F FrrZr reg_fieldrr9c |jd}|jd}||z dz}d|zdz }||kDrtd|d|d|dd|zdz }|||zz}|||z|zz}|S)aSets the bits from high_bit to low_bit (inclusive) in "reg_value" to the given value. Allows to manipulate the bits at arbitrary positions inside a register. Args: value: The value to set in the specified bit range. reg_field: The register field to update, inside the register. reg_value: The register value to modify (default is 0). Returns: The modified integer with the specified bits set. Raises: ValueError: If the value is too large to fit in the specified bit range. r@rr_z is too large to fit in z bits (max value is z).)r ValueError)rrirrrnum_bits max_valuers r set_reg_bitsrnlsq!Hooa G!A%Hh!#I yUG3H:=QR[Q\\^ _  MQ D48#$$I%$,8++I r)r)(loggingr*r"rrrtypingrrrrrrenumr volatility3r volatility3.frameworkr r #volatility3.framework.configurationr volatility3.framework.layersr.volatility3.framework.interfaces.configurationr getLoggerrrLayerExceptionrLinearlyMappedLayerrr5r=r?rBrGrZr`rnrrrrzs  ==%8</D   8 $. z00 C  f((C  L( $g ',$('$8<5Q5Qp.F.Fb''''S'r